Code download in a system having multiple integrated circuits with a jtag capability

ABSTRACT

An electronic product ( 500 ) including a first integrated circuit ( 502 ) coupled to a first memory ( 506 ) and at least a second integrated circuit ( 508, 512 ) coupled ( 516, 518, 520 ) to the first integrated circuit. The first integrated circuit loads information, such as a first code image, from the first memory into the first integrated circuit, and executes at least a portion of the first code image. In response to such code execution, the first integrated circuit reads information, such as a second code image, from the first memory and transmits that information to the second integrated circuit. The interface between the first and second integrated circuits for transmission of the information may be a test circuitry ( 522, 528, 526, 524 ) interface such as JTAG circuitry. In one embodiment program code is transferred from a single external memory through a first integrated circuit to one or more downstream integrated circuits by way of serially connected JTAG data and control pins.

The present invention relates generally to electronic systems, and moreparticularly relates to methods and apparatus for efficiently loadinginformation into a plurality of integrated circuits, each of whichrequires such information to perform its intended function.

Advances in semiconductor manufacturing technology, as well as indigital systems architecture, have resulted in the ability to design andproduce larger integrated circuits incorporating much more functionalitythan has been possible in the past. A particular class of integratedcircuits, which incorporate at least several large functional blocks toproduce a high level of functionality, is referred to as System on Chip(SoC). Such SoC integrated circuits often include one or more processorsalong with memory for storing program code that is to be executed by theprocessors, and one or more circuit blocks for implementing varioushigh-level peripheral functions.

The SoC is typically used in an electronic product, or system, thatincludes various other components. In a typical arrangement, a SoC and anon-volatile memory, such as a ROM or flash, which is external to theSoC, are mounted on a substrate, such as a printed circuit board. Inthis case, the external non-volatile memory is coupled to the SoC so asto provide program code that is loaded into the SoC for subsequent useby the one or more processors integrated thereon. In other arrangements,memory for program code may be completely or partly external to the SoC.As electronic products become more complex, a need has arisen to includemultiple SoCs in a single electronic product.

What is needed are methods and apparatus for, efficiently loadinginformation into a plurality of integrated circuits, such as SoCs, thatare included in an electronic product.

Briefly, embodiments of the present invention provide for loadinginformation from a single non-volatile external memory, into a pluralityof integrated circuits, wherein only one of the plurality of integratedcircuits is connected for memory access to the single non-volatileexternal memory.

In a further aspect of the present invention, the information loadedinto at least one of the plurality of integrated circuits comprisesprogram code that can be executed by a processor included within the atleast one integrated circuit.

In a still further aspect of the present invention, the communicationpath used for transferring program code from a single external memorythrough a first integrated circuit to a second integrated circuit iscomprised of the test pathways within each of the first and secondintegrated circuits.

FIG. 1 is a schematic block diagram of a conventional electronic productincluding a plurality of SoCs, each SoC coupled to a separate externalnon-volatile memory chip from which program code is transferred to theSoC.

FIG. 2 is a high level block diagram of an electronic product in which asingle external memory chip supplies information, such as program codeto a plurality of SoCs, in accordance with the present invention.

FIG. 3 is a schematic block diagram of an electronic product in which asingle external memory chip supplies information, such as program codeto a plurality of SoCs through a JTAG mechanism, in accordance with thepresent invention.

FIG. 4 is a schematic block diagram of an integrated circuit, suitablefor use in an embodiment of the present invention, generally showing aJTAG compliant integrated circuit, and more particularly illustratingEJTAG extensions.

FIG. 5 is a schematic block diagram of an electronic product in which asingle external non-volatile memory chip supplies information, such asprogram code to a plurality of SoCs, each SoC also having a privateexternal memory, through a JTAG mechanism, in accordance with thepresent invention.

FIG. 6 is a schematic block diagram of an electronic product in which asingle non-volatile external memory chip supplies information, such asprogram code to a plurality of SoCs, through a JTAG mechanism, inaccordance with the present invention, and each SoC is coupled to itsown external memory bus.

FIG. 7 is a flowchart of an illustrative process in accordance with thepresent invention.

FIG. 8 is a flowchart of another illustrative process in accordance withthe present invention.

Electronic products that include multiple integrated circuits, wherethose integrated circuits are themselves of the “Systems on a Chip”(SoC) variety, are becoming more and more prevalent due totime-to-market constraints. That is, a system solution that provides acertain functionality may now be realized more quickly by integratingseveral SoCs at the board level, rather than by producing a new ASIC(i.e., SoC) with the combined functionality of those multiple SoCs.Conventionally, each of such SoCs includes, among other things, aprocessor for executing program code, and a memory for storing theprogram code to be executed by that processor. In some conventionalalternative arrangements, an external memory for storing the programcode to be executed by the processor, is coupled to the SoC. Alsoconventionally, each one of such SoCs must be coupled to a separateexternal memory from which program code is loaded into the SoC. In thisconventional arrangement, each SoC is coupled to a separate memory,which adds considerably to the cost of the electronic product.

Various embodiments of the present invention provide the program code,from a single external memory, for each of the multiple SoCs in thesystem, by using an existing communication interface on each of the SoCsthat is normally used for system debugging operations. In someembodiments, the JTAG circuitry included in each of the SoCs is used toprovide the communication interface used for downloading code.

Reference herein to “one embodiment”, “an embodiment”, or similarformulations, means that a particular feature, structure, operation, orcharacteristic described in connection with the embodiment, is includedin at least one embodiment of the present invention. Thus, theappearances of such phrases or formulations herein are not necessarilyall referring to the same embodiment. Furthermore, various particularfeatures, structures, operations, or characteristics may be combined inany suitable manner in one or more embodiments.

The acronym ASIC refers to an Application Specific Integrated Circuit.

The acronym JTAG refers to the Joint Test Action Group. The Institute ofElectrical and Electronic Engineers (IEEE) has approved IEEE Standard1149.1, Test Access Port and Boundary Scan Architecture.

The acronym LSI refers to Large Scale Integration.

The acronym NVM refers to non-volatile memory, and includes any suitabledata storage means that retains data without power being applied.Examples of non-volatile memories include, but are not limited to, ROM,PROM, EPROM, and flash.

The acronym SoC refers to a System on a Chip, with SoCs being the pluralof SoC.

The acronym TAP refers to a Test Access Port.

MIPS EJTAG refers to a hardware debug facility that providesnon-intrusive debug capabilities for SoCs that include embedded MIPSarchitecture processors. A similar, but alternative arrangement,referred to as ICE, is available for the ARM processor architecture.

The terms chip, semiconductor device, integrated circuit, LSI device,monolithic integrated circuit, ASIC, SoC, microelectronic device, andsimilar expressions are sometimes used interchangeably in this field.Microelectronic device may be considered to be the broadest term,encompassing the others. With respect to these microelectronic devices,signals are coupled between them and other circuit elements viaphysical, electrically conductive connections. The point of connectionis sometimes referred to as an input, output, terminal, line, pin, pad,port, interface, or similar variants and combinations. These areconsidered equivalent terms for the purpose of this disclosure.

The term downloading is used herein to refer to the transfer ofinformation, including, but not limited to, program code, from anexternal memory to an integrated circuit, such as for example an SoC,that is either directly connected, or indirectly coupled, to theexternal memory.

Programming instructions are sometimes referred to as code. It is oftennecessary to provide data, such as, for example, constants, along withprogramming instructions to construct a working program. Similarexpressions include, but are not limited to, program code, software,firmware, and microcode.

A JTAG compliant device includes pins for clock, input data, outputdata, and mode selection, referred to, respectively, as TCK, TDI, TDO,and TMS. TCK refers to Test Clock Input which is a terminal of the JTAGcompliant device that receives a clock signal separate from the systemclock. TDI refers to a Test Data In which is a terminal through whichdata is shifted into the JTAG compliant device. TDO refers to Test DataOut which is a terminal through which data is shifted out of the JTAGcompliant device. TMS refers to Test Mode Select which is a terminalwhich receives data for determining which of one or more test modes thein which the JTAG compliant device is to operate. A JTAG compliantdevice may be any type of integrated circuit such as, for example, amicroprocessor, an ASIC, or a SoC. A JTAG compliant device may alsoinclude a pin to receive a low active reset signal, referred to asTRST#. JTAG compliant devices include a boundary scan register and a TAPcontroller. The TAP controller is a state machine that controls the JTAGfunctions. The boundary scan register is made up of a number of seriallyconnected bits where each of those bits is also coupled to digital pinsof the JTAG compliant device. JTAG compliant devices may also includeother registers, such as, a data register, an instruction register, anda bypass register.

A SoC with EJTAG uses the 5-pin JTAG interface, which is specified inthe IEEE 1149.1 JTAG standard, for communication with other components.The EJTAG circuitry also provides a means of directly controlling thebehavior of the embedded processor. Internally, the SoC with EJTAGincludes circuitry for, among other things, accessing the address anddata busses which are typically used by the embedded processor, programmemory, and other functional blocks included within the SoC.

Various embodiments of the present invention use the existing debugcapabilities of a SoC in a production environment to reduce the overallcost of a complete system that includes two or more SoCs.Conventionally, each SoC has a counterpart external memory from which itboots up. Some embodiments of the present invention store the codeimages for each SoC of a multi-SoC electronic product, in a singleexternal memory which is interfaced to a single one of the SoCs. Thecode image for each of the downstream SoCs is transferred thereto via aninterface between the SoC that is interfaced to the external memory andeach of the downstream SoCs.

Referring to FIG. 1, a conventional electronic product 100 is shown.Conventional electronic product 100 includes a printed circuit board102, having first, second, and third SoCs 104, 108, 112, and first,second, and third non-volatile memories 106, 110, 114 disposed thereon.SoCs 104, 108, 112 are typically integrated circuits having at least thecircuitry necessary for providing a processor for executing programminginstructions, and a memory for storing programming instructions.Non-volatile memories 106, 110, 114 are coupled, respectively, to first,second, and third SoCs 104, 108, 112 such that code may be transferredbetween each respectively coupled SoC and non-volatile memory. It can beseen that in the conventional approach of FIG. 1, each SoC requires aseparate non-volatile memory and a pathway to access those separatenon-volatile memories. These components, as well as, the space and powerthey require, increase the manufacturing and operating costs of anelectronic product constructed in this way.

Referring to FIG. 2, an electronic product 200 in accordance with thepresent invention is shown. Electronic product 200 includes a substrate202. Substrate 202 is typically a printed circuit board, but may be anysuitable material or construction for supporting integrated circuits, orother components, which may be disposed thereon. As shown in FIG. 2, afirst non-volatile memory 206, a first SoC 204, a second SoC 208, and athird SoC 210 are disposed on substrate 202. SoCs 204, 208, 210, mayhave the same hardware facilities or different hardware facilities,although in typical embodiments, these have different hardwarefacilities for implementing different functions. By way of example andnot limitation, a first SoC may include hardware facilities forimplementing a cable modem interface, while a second SoC may includehardware facilities for implementing an MPEG decoder. In thisillustrative example, SoCs 204, 208, 210, each include a MIPSarchitecture processor and EJTAG debug facilities. It will beappreciated by those of ordinary skill in the art having the benefit ofthis disclosure that other debug facilities may be used as long asaccess to the embedded memory of the SoC is provided.

First non-volatile memory 206 and first SoC 204 are connected such thatSoC 204 can access, i.e., read, the contents of first non-volatilememory 206. Another way of describing this is to say that first SoC 204includes an external memory interface that is connected to the externalmemory (i.e., non-volatile memory 206). SoC 204 is coupled to SoC 208 tocommunicate data from SoC 204 to SoC 208. Similarly, SoC 208 is coupledto SoC 210 to communicate data from SoC 208 to SoC 210. Such aconfiguration permits data, such as, for example, code images, to betransferred from non-volatile memory 206 via an external memoryinterface to SoC 204, via the external memory interface and through SoC204 to SoC 208, and via the external memory interface, through SoC 204,and through SoC 208 to SoC 210.

Referring to FIG. 3, an electronic product 300 in accordance with thepresent invention is shown. Electronic product 300 of FIG. 3 is similarto that shown in FIG. 2, but more particularly illustrates signalpathways for implementation with a JTAG interface for transferring codeimages from a single external memory to each of a plurality ofintegrated circuits wherein only one of the plurality of integratedcircuits is coupled to read the external memory. A first non-volatilememory 206, a first SoC 204, a second SoC 208, and a third SoC 210 aredisposed on a substrate 302. JTAG clock, reset, and mode select signals(TCLK, TRST#, and TMS) are coupled in common to each of first, second,and third SoCs 204, 208, 210. These signals are driven by first SoC 204during the code download operation of the present invention, whereasthese signal would conventionally be driven from outside signal sourcesfor conventional uses of JTAG circuitry. First non-volatile memory 206and first SoC 204 are connected such that SoC 204 can access, i.e.,read, the contents of first non-volatile memory 206. SoC 204 is coupledto SoC 208 to communicate data from SoC 204 to SoC 208. Moreparticularly, an output terminal 304 of SoC 204 is coupled to an inputterminal 306 of SoC 208 by a conductive pathway 308. In thisillustrative embodiment, output terminal 304 is a JTAG test data output(TDO) pin, and input terminal 306 is a JTAG test data input (TDI) pin.Similarly, SoC 208 is coupled to SoC 210 to communicate data from SoC208 to SoC 210. More particularly, an output terminal 310 of SoC 208 iscoupled to an input terminal 312 of SoC 210 by a conductive pathway 314.In this illustrative embodiment, output terminal 304 is a JTAG test dataoutput (TDO) pin, and input terminal 306 is a JTAG test data input (TDI)pin. Such a configuration permits data, such as, for example, codeimages, to be transferred from non-volatile memory 206 via an externalmemory interface to SoC 204, via the external memory interface andthrough SoC 204 to SoC 208, and via the external memory interface,through SoC 204, and through SoC 208 to SoC 210. Circuitry internal toSoCs 208, 210 control the loading of the program code, for example, intotheir internal memories.

Still referring to the illustrative embodiment shown in FIG. 3, it isnoted that there may optionally be a connection (not shown) between atest data output pin of SoC 210 and a test data input pin of SoC 204 tocreate a return path. Such a connection provides for situations in whichSoC 204 is required to determine the status of the various downstreamSoCs.

Referring to FIG. 4, a high-level schematic block diagram of a JTAGcompliant IC, which includes EJTAG functionality, is shown. Moreparticularly, a SoC 400, which includes a CPU 402, debug registers 404,system memory 406 for storing at least program code, a peripheralfunctional block 408, and an EJTAG block 410, is shown. EJTAG block 410includes a TAP controller 412, instruction, data, control, and boundaryscan registers 414, a direct memory access (DMA) module 416, and aprocessor access module 418. SoC 400 further includes address/data bus420 to which are coupled CPU 402, debug registers 404, system memory406, DMA module 416, and processor access module 418. It is noted that:in some embodiments the system memory may be located off-chip; the DMAmodule is not necessarily included in all embodiments; and that someembodiments may include direct control and/or status connections betweenthe EJTAG circuitry and the processor. TAP controller 412 has inputterminals for receiving JTAG clock, reset, mode select, and data inputsignals, and further has an output terminal for transmitting a dataoutput signal. Such an arrangement provides a mechanism for transferringinformation into and out of the system memory.

Referring to FIG. 5, a schematic block diagram of an electronic product500 that includes a single non-volatile memory and several SoCs, witheach SoC having a connection to its own private external memory. In thisillustrative embodiment, a SoC 502, capable of operating as an EJTAGMaster device, is coupled to a non-volatile memory 504. SoC 502additionally has an input terminal coupled to a node 522 from which itreceives a JTAG Compliance Enable signal. The JTAG Compliance Enablesignal is used in connection with changing the operational mode of SoC502 between JTAG master and JTAG slave. NVM 504 may contain program codeand/or other data to be loaded into a plurality of the SoCs inelectronic product 500. An external memory 506 is coupled to SoC 502.External memory 506 is capable of storing, among other things, programcode and/data which is downloaded from NVM 504. In a similar fashion, asillustrated in FIG. 5, SoCs 508, 512, are respectively coupled to theirown private external memories 510, 514. SoCs 508, 512 are capable ofoperating as EJTAG Slave devices. Additionally, a communication pathway516, for providing control signals from the EJTAG Master device to theEJTAG Slave device, is coupled between SoCs 502, 508, and 512 as shown.It is noted that these control signals (such as for example, clock,reset, and mode) may be driven by an external source, such as a testerfrom port 526 when electronic product 500 is suitably configured tooperate in a test mode. Communication pathway 516 typically provides forcommunication of signals such as, for example, a clock signal, a resetsignal, and a mode signal. Also shown in FIG. 5 is a pathway 518 forconnecting a test data output terminal of SoC 502 to a test data inputterminal of SoC 508; and a pathway 520 for connecting a test data outputterminal of SoC 508 to a test data input terminal of SoC 512. It isnoted that the test data output of SoC 512 may be observed at port 524,and that the test data input of SoC 502 may be driven from port 528.Furthermore, it is noted that, a return loop may be created connectingthe test data output of SoC 512 to the test data input of SoC 502.

In operation, illustrative electronic product 500 may transferinformation, such as program code and/or data from NVM 504 to privateexternal memories 506, 510, and 512 under control of the EJTAG Masterdevice which utilizes the JTAG serial data pathways included in SoCs502, 508, and 512. It is noted that, in various embodiments, SoCs 502,508, and 512 may each have some amount of memory incorporated withinthemselves, and in some embodiments these internal memories may alsostore program code and/or data.

Referring to FIG. 6, a schematic block diagram of an electronic product600 that includes a single non-volatile memory and several SoCs, witheach SoC having a connection to its own memory bus is shown. Thisexemplary embodiment illustrates an advantage of the present inventionwherein non-volatile memory is removed from the memory bus therebyreducing bus loading and allowing for higher speed operation of thememory devices coupled to the memory bus. Another advantage of such anarrangement is that the memory controller logic of the SoCs issimplified because the SoCs only need to interface to RAM, rather thanboth RAM and NVM (which may have different control signal specificationsfor memory access). More particularly, a SoC 602 is coupled to a NVM604, which is capable of operating as an EJTAG Master device. In thisillustrative embodiment, NVM 604 is a flash memory that includes thecircuitry to be an EJTAG Master device, even though it does not have aprocessor, or CPU, integrated therein. SoC 602, along with SoCs 612 and614 are each respectively coupled to a memory bus 606 a, 606 b, 606 c.Memory devices 608 a, 610 a; 608 b, 610 b; and, 608 c, 610 c, are showncoupled respectively to memory buses 606 a, 606 b, 606 c. It is notedthat there are a wide variety of commercially available memoryarchitectures, and memory access protocols, however memory devices 608a, 610 a; 608 b, 610 b; and, 608 c, 610 c may be any suitable memoriessuch as, but not limited to, static random access memories or dynamicrandom access memories. It is further noted that although two memorydevices are shown coupled to the memory bus, the present invention isnot limited to any particular number of such devices.

Still referring to FIG. 6, communication path 616 is shown coupledbetween EJTAG Master NVM 604 and SoCs 602, 612, and 614. Communicationpath 616 is suitable for providing control signals such as, but notlimited to, a clock signal, a reset signal, and a mode signal. Acommunication path 618 couples a test data output terminal of SoC 602 toa test data input terminal of SoC 612. A communication path 620 couplesa test data output terminal of SoC 612 to a test data input terminal ofSoC 614.

It is noted that the present invention may alternatively be embodied ina configuration similar to that shown in FIG. 6, with the exception thateach SoC accesses volatile memory over a common memory bus rather thanprivate memory buses.

Referring to FIG. 7, an illustrative process in accordance with thepresent invention is shown. In a first operation 702, a first programcode is transferred from a first memory to a first integrated circuit.The first memory is typically a single chip, and is also typically anon-volatile memory chip, such as for example a Read-Only-Memory (ROM)or a flash. In accordance with the present invention, the first memorymay also be implemented as multiple stacked memory chips that areaddressable as a single package or unit. The first program codetypically includes a plurality of instructions that are executable by aprocessor within the first integrated circuit. The first program codemay also include data, i.e., non-executable information, that can beused by a processor on the first integrated circuit. The processor onthe first integrated circuit may be of any suitable architecture. Oneexample of a processor architecture that may be used in an SoC inaccordance with the present invention is the MIPS architecture. However,the present invention is not limited to any particular processorarchitecture. The first integrated circuit may implement any arbitraryfunction; may be of a class of integrated circuits referred to as anSoC; and may be an SoC that includes JTAG test circuitry (e.g., boundaryscan register, TAP controller, mode select register, bypass register,etc.). The first IC includes a memory in which program code may bestored (although as noted above, alternative embodiments have thismemory external to the IC). The first integrated circuit typicallyincludes a pathway, such as that provided by EJTAG circuitry, thatallows information to be transferred into and out of the memory. Thefirst program code is stored 704 in the first IC. As shown in FIG. 7, asecond program code is transferred 706 from the first memory to thefirst IC, and the second program code is transmitted 708 from the firstIC to a second IC that is coupled to the first IC. The second IC mayimplement any arbitrary function; may be of a class of integratedcircuits referred to as an SoC; and may be an SoC that includes a JTAGtest circuitry interface for communication. The second program code isstored 710 in the second IC. It is noted that one or more additionalintegrated circuits may receive code from the first memory by way of thefirst integrated circuit, and any intermediately coupled integratedcircuits in accordance with the present invention. The transmission ofthe second program code from the first IC to the second IC may beaccomplished by any suitable interface arrangement. In some embodimentsof the present invention, the interface arrangement is that provided bythe JTAG test circuitry included in the first and second integratedcircuits. It is noted that the transfer of data may, but is not requiredto, take place in a pipelined fashion, that is a portion of the data tobe transferred is moved and then the process is iterated until all therequired data has been transferred.

Referring to FIG. 8, another illustrative process in accordance with thepresent invention is shown. In a first operation 802, a first programcode is transferred from a first memory to a first IC. The first memoryis typically a single-chip non-volatile memory IC. The first programcode typically includes a plurality of instructions that are executableby a processor incorporated within the first IC. The first program codemay also include data. The first IC may implement any arbitraryfunction; may be of a class of integrated circuits referred to as anSoC; and may be an SoC that includes JTAG test circuitry. The first ICincludes a memory in which program code may be stored. The first programcode is stored 804 in the first IC. The first IC then executes 806 atleast a portion of the first program code. In response to the executionof at least a portion of the first program code in the first IC, asecond program code is transferred 808 from the first memory to thefirst IC. In further response to the execution of at least a portion ofthe first program code, the second program code is transmitted 810 fromthe first IC to a second IC that is coupled to the first IC. The secondIC may implement any arbitrary function; may be of a class of integratedcircuits referred to as an SoC; and may be an SoC that includes JTAGtest circuitry. In the illustrative embodiment of the present invention,the second program code is serially shifted out of the first IC via itsJTAG data output pin, and serially shifted in to the second IC via theJTAG data input pin of the second IC. The second program code is stored812 in the second IC such that it may be executed by a processorincluded within the second IC. It is noted that one or more additionalintegrated circuits may receive code from the first memory by way of thefirst IC, and any intermediately coupled integrated circuits inaccordance with the present invention.

In one illustrative embodiment, a first IC loads program code from anexternal memory and then boots up into a state from which it can beginto download code into one or more downstream integrated circuits towhich it is coupled (directly or indirectly). In such an embodiment thefirst IC may initialize a memory controller of a second IC, downloadcode into the memory of the second IC, and set the embedded processor ofthe second IC running from the memory of the second IC. Similarly, thefirst IC may download code to, and start, each of a plurality ofdownstream ICs.

In an alternative illustrative embodiment, the first IC loads programcode from an external memory but only boots up to a limited extent,rather than to its completely functional mode, before it begins theprocess of downloading code to downstream integrated circuits. After,one or more downstream devices have been loaded with program code, thefirst integrated circuit may return to its boot up operation. Byinitiating parallel operations, the total system boot up time may bereduced, since downstream devices have begun their respective boot upoperations prior to the first IC completing its boot up operation.

In a further alternative embodiment, code may be downloaded into two ormore downstream devices concurrently.

Although various illustrative embodiments of the present invention havebeen described in terms of electronic products having a plurality ofintegrated circuits that include processors, and the downloading ofprogram code to those integrated circuits for execution by theprocessors, it is noted that the present invention is more widelyapplicable. For example, rather than program code suitable forexecution, one or more of the ICs in an illustrative electronic productmay receive data or control information. As noted above, the downstreamintegrated circuits that receive information from a single memory inaccordance with the present invention interface with another IC disposedintermediate the memory and the IC receiving the information.Additionally, although a JTAG-based interface is described inillustrative embodiments of the present invention, any suitableinterface may be used for the data transfer operations between thesingle external memory and the various integrated circuits included inthe electronic product.

It is noted that the single external memory chip referred to in variousillustrative embodiments of the present invention, may additionally havecircuitry included thereon which implements any arbitrary functionality.

Various embodiments of the present invention combine existing hardwarecapabilities of a plurality of individual integrated circuits, such asfor example JTAG-compliant SoCs, in a novel manner to provide systemsand methods to reduce the size, cost, and power consumption, ofelectronic products.

In some embodiments, the JTAG debug capabilities of individualintegrated circuits are combined in a production environment such thatcode images for each IC in a system can be stored in a single flashmemory, attached to an EJTAG master enabled device, and downloaded intoeach target device once the EJTAG master device has booted up.

It is to be understood that the present invention is not limited to theembodiments described above, but encompasses any and all embodimentswithin the scope of the subjoined claims.

1. A method of transferring programming instructions from a first memorydisposed on a substrate, to a plurality of integrated circuits (ICs)disposed on the substrate, comprising: a first one of the plurality ofICs accessing the first memory, retrieving a first set of programminginstructions, and storing the first set of programming instructionswithin the first one of the plurality of ICs; and the first one of theplurality of ICs accessing the first memory integrated circuit,retrieving a second set of programming instructions, and transmittingthe second set of programming instructions to a second one of theplurality of ICs.
 2. The method of claim 1, wherein the first and secondones of the plurality of ICs each comprises a processor capable ofexecuting, respectively, the first and second sets of programminginstructions.
 3. The method of claim 2, further comprising the first oneof the plurality of ICs executing at least a portion of the first set ofprogramming instructions.
 4. The method of claim 3, wherein executing atleast a portion of the first set of programming instructions occursprior to transmitting the second set of programming instructions to asecond one of the plurality of ICs.
 5. The method of claim 2, furthercomprising the first one of the plurality of ICs accessing the firstmemory, retrieving a first set of data, and storing the first set ofdata within the first one of the plurality of ICs; and the first one ofthe plurality of ICs accessing the first memory, retrieving a second setof data, and transmitting the second set of data to a second one of theplurality of ICs.
 6. The method of claim 3, wherein the substratecomprises a printed circuit board.
 7. The method of claim 3, whereintransmitting comprises serially shifting data out from the firstintegrated circuit and concurrently shifting data in to the secondintegrated circuit.
 8. The method of claim 7, further comprisingtransmitting control information from the first integrated circuit tothe second integrated circuit prior to transmitting the second set ofprogramming instructions to a second one of the plurality of ICs.
 9. Themethod of claim 8, wherein the control information directs the secondone of the plurality of ICs to receive a subsequent transmission ofprogramming instructions.
 10. In a system including a plurality ofintegrated circuits (ICs) disposed on a printed circuit board, each ICcomprising a memory for storing at least programming instructions, eachfurther comprising a processor coupled to the memory for executingprogramming instructions stored in the memory; the system furtherincluding a single non-volatile memory disposed on the printed circuitboard and coupled for memory access to only a first one of the pluralityof ICs, a method of downloading code from the single non-volatile memoryto each of the plurality of ICs, comprising: receiving, at a first oneof the plurality of ICs, a first set of data from the singlenon-volatile memory; storing the first set of data in the memory of thefirst one of the plurality of ICs; receiving, at the first one of theplurality of ICs, a second set of data from the single non-volatilememory; transmitting the second set of data from the first one of theplurality of ICs to the second one of the plurality of ICs; and storingthe second set of data in the memory of the second one of the pluralityof ICs; wherein the first and second sets of data comprise program code.11. The method of claim 10, further comprising: executing, in the firstIC, at least a portion of the program code in the first set of data;receiving, at the first one of the plurality of ICs, a third set of datafrom the single non-volatile memory; transmitting the third set of datafrom the first one of the plurality of ICs to a third one of theplurality of ICs; and storing the third set of data in the memory of thethird one of the plurality of ICs;
 12. The method of claim 10, whereintransmitting the second set of data from the first one of the pluralityof ICs to the second one of the plurality of ICs comprises seriallyshifting data out of the first one of the plurality of ICs via an outputterminal; wherein the output terminal is coupled to an input terminal ofthe second one of the plurality of ICs, the input terminal coupled tocircuitry within the second one of the plurality of ICs that is adaptedto receive serial data.
 13. The method of claim 12, further comprisingproviding transmitting control information from the first one of theplurality of ICs to the second one of the plurality of ICs prior totransmitting the second set of data.
 14. The method of claim 13, whereincontrol information is transmitted in accordance with a JTAG standard ofcommunication.
 15. An electronic product, comprising: a first integratedcircuit having a first processor, a first internal memory, a firstserial communication interface, and an external memory interface; anexternal memory coupled to the external memory interface; a secondintegrated circuit having second processor, a second internal memory,and a second serial communication interface, the second serialcommunication interface being coupled to the first serial communicationinterface; wherein the first integrated circuit, the external memory,and the second integrated circuit are disposed on a substrate.
 16. Theelectronic product of claim 15, wherein the first processor is coupledto the first internal memory, the first internal memory is adapted toreceive a first code image, the second processor is coupled to thesecond internal memory, the second internal memory is adapted to receivea second code image, and the external memory is a non-volatile memoryencoded with the first and second code images.
 17. The electronicproduct of claim 16, wherein the first integrated circuit includes afirst hardware facility for performing at least a first function, andthe second integrated circuit includes a second hardware facility forperforming at least a second function, and the first and secondfunctions are different.
 18. The electronic product of claim 17, furthercomprising a third integrated circuit, having a third processor, a thirdinternal memory, and a third serial communication interface, the thirdserial communication interface being coupled to the second serialcommunication interface, the third processor coupled to the thirdinternal memory, the third internal memory is adapted to receive a thirdcode image, and the external memory further encoded with the third codeimage.